ISC processors rely (to some extent) on on?chip registers for their performance increase. A cache memory can provide a similar level of performance increase without restricting the programmer to a fixed set of registers. Discuss the validity of this statement.

What will be an ideal response?

Memory accesses can take orders of magnitude longer than register accesses. Because RISC style processors have far more registers than CISC processors, it is possible to operate on a subset of data stored within the chip and to reduce memory accesses.

However, cache memory, which is a copy of some frequently?used memory, can reduce the memory access
penalty by keeping data in the on?chip cache.

One argument in favor of cache is that it is handled automatically by the hardware. Registers have to be allocated by the programmer or the compiler. If the number of registers is limited, it is possible that the on?chip registers may be used/allocated non?optimally.

Cache memory also has the advantage that it supports dynamic data structures like the stack. Most computers do not allow dynamic data structures based on registers (that is, you can’t access register ri, where i is an index). The Itanium IA64 that we discuss in Chapter 8 does indeed have dynamic registers.