In terms of hardware resources needed (number of new processor registers and additional circuitry to generate the physical memory address given a CPU generated address) compare base and limit register solution with a paged virtual memory solution.

What will be an ideal response?

Base and limit needs two registers to store base and limit values. Also need an ALU type device to determine if limit has been exceeded and an adder to add the base register to the desired address. Paged virtual memory solutions minimally require a register to point to the page table and a register in which to form the physical address. Realistically such system will probably include a TLB which is quite a complex device: numerous registers and operational logic.