Design a D flip?flop using only an RS latch and simple gates. Include a circuit diagram, timing diagram, and truth table in your answer.

What will be an ideal response?

There are several ways of tackling this problem. Let’s start with an RS latch made from NOR gates. This has an R input and an S input that can be used to set or reset the flip?flop. If both inputs are 0, the outputs remain the same. If R = 1, S = 0, Q is cleared and if S = 1, R = 0, Q is set. The state S = R = 1 should be avoided.



So, we use two AND gates to feed the R,S inputs. One input to of each of the two AND gates is the clock. When the clock is 0, the AND gates both have 0 outputs and R = S = 0. Consequently Q remains what it was, unchanged.



When the clock is 1, the AND gates are enabled. One input is D and the other NOT D (via an inverter). This assumes that R,S = 0,1 or 1,0. Consequently, the Q output is set if D is 1 and cleared if D is 0. This is a D flipflop.