A processor with memory management has a 4K page size. It has a 32K cache memory with 16?byte cache lines. In order to speed up memory access, you decide to arrange the cache so that the cache is accessed at the same time a logical to physical address translation is taking place. In order for the scheme to work, what level of associativity must be implemented?
What will be an ideal response?
The cache must look like a memory page to the computer; that is, it must be spanned by address bits A00 to A11
(i.e., 4K). The memory is actually 8 x 4K = 32K which corresponds to an associativity of 8.
Computer Science & Information Technology
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A function's ________ defines the rules by which the function operates
Fill in the blank(s) with correct word
Computer Science & Information Technology
What is the value of ANSWER after the instructions corresponding to the following pseudocode are executed?
``` COUNT = 1 SUM = 3 DOWHILE COUNT ? 0 SUM = SUM + COUNT COUNT = COUNT - 1 ENDDO ANSWER = SUM ``` a) 3 b) 4 c) 5 d) 6
Computer Science & Information Technology