A processor executes an instruction in the following six stages. The time required by each stage in picoseconds (1,000 ps = 1 ns) is given for each stage.

IF instruction fetch 300 ps
ID Instruction decode 150 ps
OF Operand fetch 250 ps
OE Execute 350 ps
M Memory access 700 ps
OS Operand store (writeback) 200 ps

a. What is the time to execute an instruction if the processor is not pipelined?
b. What is the time taken to fully execute an instruction assuming that this structure is pipelined in six stages
and that there is an additional 20 ps per stage due to the pipeline latches?
c. Once the pipeline is full, what is the average instruction rate?
d. Suppose that 25% of instructions are branch instructions that are taken and cause a 3?cycle penalty, what is
the effective instruction execute time?

a. Add up the individual times: 300 + 150 + 250 + 350 + 700 + 200 = 1950ps = 1.950ns
b. The longest stage is 700 ps which determines the clock period. With 20 ps for the latches, the time is 720 × 6
= 4320 ps = 4.32 ns.
c. One instruction per clock; that is every 720 ps.
d. 75% of instructions are not taken branches and these take on average 0.75 × 720 ps = 540 ps. 25% are taken
branches that take 0.25 × 3 × 720 ps = 540 ps. The total time is 540 + 540 =1080 ps.