The Instruction Fetch is implemented in the text with first 4 states and then three. What would have to be done to the datapath to make it two states long?

What will be an ideal response?

In order to implement the Instruction Fetch in 2 states, there would have to be a second bus incorporated into the datapath, that could either take the MEM[MAR] to the IR in the first state, or could take A+1 to the PC in the second state, therefore combining 2 of the present states into 1, eliminating 1 state overall.