You are redesigning an existing RISC?style pipelined processor to make it a three?way superscalar processor that permits three instructions to be executed at the same time.

a. Do you expect the new processor to achieve three instructions per clock?
b. What level of design complexity do you expect the new processor to have in comparison with the pipelined version?

a. If the superscalar processor has three execution units, it can achieve a maximum throughput of three instructions per clock. However, if there is instruction dependency, it may not be possible to execute three instructions in parallel at every clock. Moreover, most superscalar processors do not have identical processing units; for example, some are integer, some floating?point, some branch, some load/store, or any combination of these. Consequently, it may be impossible to execute three instructions in the same clock if they cannot find three execution units to accommodate them.
b. You make a pipelined processor by taking the diagram of a non?pipelined processor, drawing parallel lines, putting registers where the lines are and that’s it. OK, so I exaggerated a bit. However, pipelining is largely about dividing the flow of an instruction through a processor and breaking it into chunks, the stages. Superscalar computing is rather more complex. The instructions have to be examined, renamed and reordered for execution. They have to be issued and executed. Moreover, they have to be retired in the correct order to ensure that an interrupt does not take place when instruction i + 1 has been completed and stored, whereas instruction i has not been completed. Consequently, designing a three way superscalar
processor is probably more than three times as complex as designing the pipelined processor.