In a 5-stage pipelined processor, upon a page fault, what needs to happen in hardware for instruction re-start?
What will be an ideal response?
If the page fault occurs during instruction fetch the pipeline should be drained, that is the instructions already in execution in the pipeline should be allowed to complete. Then, the page fault is serviced and the instruction restarted.
If the page fault occurs in MEM (i.e. LW or SW) the instructions in IF, ID, EX can be squashed since they will not have made any persistent changes to the register file, etc. Then the page fault may be serviced and the instruction restarted.
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